Freescale Semiconductor /MKW20Z4 /XCVR /TX_DIG_CTRL

Radio DFT Modes

0 (000): Normal Radio Operation. DFT not engaged.

1 (001): Pattern Register Mode. TX DFT Modulation Pattern Register is shifted out as the transmission data stream. Note that the DFT_EN bit must be set.

2 (010): LFSR Data Mode. TX LFSR is used as the transmission data stream. Note that the LFSR_EN bit must be set.

3 (011): LFSR Symbol Mode. TX LFSR is used to create 802.15.4 symbols which are then converted to Chips and transmitted. Note that the LFSR_EN bit must be set.

4 (100): Not implemented on Apache 1.0, future use will allow a package pin to be used as the source of the TX data stream. Note that the DFT_EN bit must be set.

5 (101): Constant Frequency Mode. No data modulation is done, Radio transmits at the channel frequency selected.

6 (110): LFSR Tone Mode. TX LFSR is used to select the DFT Tone register to transmit, LFSR_EN bit must be set.

7 (111): Manual Tone Mode. TONE_SEL is used to select the DFT Tone register to transmit.

Radio DFT Mode Enable

DFT LFSR Length

0 (000): LFSR 9, tap mask 100010000

1 (001): LFSR 10, tap mask 1001000000

2 (010): LFSR 11, tap mask 11101000000

3 (011): LFSR 13, tap mask 1101100000000

4 (100): LFSR 15, tap mask 111010000000000

5 (101): LFSR 17, tap mask 11110000000000000

DFT LFSR Enable

DFT Clock Selection

0 (000): 62.5 kHz

1 (001): 125 kHz

2 (010): 250 kHz

3 (011): 500 kHz

4 (100): 1 MHz

5 (101): 2 MHz

6 (110): 4 MHz

7 (111): Clock is off

DFT Tone Selection

0 (00): DFT Tone 0

1 (01): DFT Tone 1

2 (10): DFT Tone 2

3 (11): DFT Tone 3

Oversample Clock Capture Polarity

0 (0): Selects Even clock cycle

1 (1): Selects Odd clock cycle, a one cycle delay

Data Padding Pattern Select

0 (0): Selects DATA_PADDING_PATTERN_0 as the source for data padding

1 (1): Selects DATA_PADDING_PATTERN_1 as the source for data padding

GFSK Frequency Word Adjustment